Cadence Skill 论坛




查看: 659|回复: 35

[SKILL下载] Cadence Skill打包下载,附说明

发表于 2018-2-8 11:03:50 | 显示全部楼层 |阅读模式

assembly.ilAdd assembly reference designators
ruler.ilAdd assembly rulers
Auto_Balancing.ilAdd filled rectangles on etch layer to provide balance during plating process
addpinuse.ilAdd pinuse codes from schematic as Allegro properties
via_prop.ilAdd a property to all vias on a net at once.
fcircle.ilAdd a filled circle to the active layer.
text_add.ilAdd text variables to the brd drawing automatically
align_sym.ilAlign symbols
add_symbol.ilAllows user to add a symbol to the design (For Allegro 14.0)
pickdata.ilAllegro to Capture backannotation of pick and place data
cds2f.ilAllegro to Fabmaster extraction utility
zrconnections.ilAPD - Graphical interface to create the IO connections file used by ZRouter
add_device_label.ilAssign DEVICE_LABEL property to components
Associate_Components.ilAssociate ICs and I/Os with bypass capacitors
jbhEditBoard.ilBuild a list of board files
qfp_pitch.ilCalculate QFP pitch
cwidth.ilChange Cline Widths /Layer/Width
component_changes.ilCheck component changes between boards
via_pcs_check.ilCheck vias on net against the vias listed in the constraint set
dangling_lines.ilCheck the status of the dangling line report
Symbol_Check.ilCheck if symbols exist
conv.ilConvert between mils and mm
cnv_height.ilConvert text height in mils to match the database units
show_height.ilCopies the 14.x PACKAGE_HEIGHT_MIN/MAX properties to visible text for display and printing
shape_push.ilCopy Shape to New Class or Subclass
smd_pad_count.ilCount SMD pads in a design
bbv_xsection.ilCreate a graphical image of the board cross section showing via structures
rep_bom_ignore.ilCreate a report and add it to your report lists
utl_sclass.ilCreate a list of subclasses for given class
runalgrplt.ilCreate an Allegro plot
mkdev.ilCreate device files for use with third party netlist implementations
Create_Thermal_Flash.ilCreate Thermal Flash
clinecut.ilCut Clines By a Graphical Window Selection
scalpel.ilCut a channel through clines by drawing a path through them.
cutshape.ilCut/Split power rings in APD Package Designs
prtobj.ilDebugging aid which recursively dumps dbid info to a file in hierarchical format
dh_dummy_net.ilDehighlight all Dummy nets in a design
del_unconn.ilDelete unconnected shapes in 8.1 - Source code
rm_nc_via.ilDelete all vias not on a net
del_fp_prop.ilDelete Signal Integrity FP_* properties from Allegro symbols
Find_DRC.ilDisplay all DRC markers for a layer
drc_walk.ilDisplays list of DRCs in a design and lets you "walk through" the list
datasheet.ilDisplay utility for Datasheets using a URL
pdi_vis.ilDisplay visibility control
utl_distance.ilDistance between 2 pts or from 0,0
draw_targets.ilDraw targets to line up paper/film plots
etch_visibility.ilEtch visibility
comp_hght_rep.ilExtract component height to a file
ipc_356.ilExtract a netlist in IPC-D-356 format
solder_paste.ilExtract solder paste information
bdct.zipFills class PACKAGE GEOMETRY/BODY_CENTER and draws circle with two diagonals in center of symbol
find_dlines.ilFind all dangling clines and dangling lines
mot_find_stubs.ilFind and identify stubs
Find_Component.ilFind components from list
height_check.ilFind components over, under or equal to a user specified height value
show_library.ilFind library path of each Allegro symbol and create a report
ood_shapes.ilFind out of date dynamic shapes in 15.0 and later
flare_conn.ilFlare connects into vias and pins
cdwIsPointInsideCircle.ilFunction to determine whether a target point is within a circle
replay.ilGUI to display scripts and replay them with a mouse click
hl_npe.ilHighlight Missing Pin Escapes Skill 8.1
hl_ntp.ilHighlight Nets and Pins without Test Probes
highlight_connected.ilHighlight only connected elements in a design
highlight_padstack.ilHighlight padstacks from a list of component pin/via padstacks, and a list of drill sizes
defineclass.zipInitialize PADPATH variable for the manufacturing class you select
net_editor.ilInteractive Net List Editor
vcListBuilder.ilList building utility
listratt.ilList all rat T points in a design
thermal.ilMake a list of all the thermal flashes used in a padstack library
slots.ilMake a list of all slots used in a padstack library
padinshape.zipMerge Cshapes with pads
Mirror_Text.ilMirror text
nclegend_list.ilNCLEGEND List all NCLEGEND- subclasses in a design.
NCP_drc.ilPlace DRC markers on Device Pins that are missing a netname
place_list.ilPlace by List
place_symbols.ilPlace symbols and reference designators
utl_ptaccur.ilPrint number or point in design db accuracy
myredraw.zipRedraws one or more objects in a different class with the same coordinates; transforms clines into shapes
killallxdrc.ilRemove all externally generated DRCs from the design
strip_bad_fillet_props.ilRemove fillet properties on clines that are not actually fillets
Rename_Ref_Des.ilRename reference designators
film_reorder.ilReorder artwork films in the artwork control form
replace_via.ilReplace Via padstack by window
upd_fe_height.ilReplace PACKAGE_HEIGHT_MAX with value of HEIGHT property from ConceptHDL
3d_length.ilReport 2d bonding wire to 3d length
dp_rep.ilReport diff pair nets in a design.
list1esc_length.ilReport first escape from pin, for Fully Buffered DIMM Design rule
check_short_segs.ilReport short cline segments that are contained within the pad.
build_ver.ilReport the product and version information of the currently running tool
no_drc.ilReport and highlight pins with the NO_DRC property
lfsViewReports.ilReport and Log File Viewer
single_pin_net_check.ilReport and highlight single pin nets.
autosize.ilResize the drawing extents to match database objects
dfa_assembly.ilRun DFA clearance checks referenced to the assembly subclass
set_refdes.ilSave refdes locations from one file and read into another
vc_SetOrigin.ilSet the design origin using mouse selection
component_height.ilShow component heights
autosilkUtils.ilSilkscreen violation checking utility
tekTechFileXML.ilTechfile - Module to parse and import an XML Techfile
rep_ucshape.ilUnconnected shape report
mirrorvia.ilUtility to unmirror vias in a design.
save_shape_drc.ilView DRC locations during shape cleanup after autovoid
cdw_axlLineXLine.ilWorkaround for the SKILL axlLineXLine() function which fails for vertical and horizontal segments


发表于 2018-2-8 14:04:16 | 显示全部楼层
发表于 2018-2-8 15:51:25 | 显示全部楼层
这都是什么skill啊   下载来看看
发表于 2018-2-8 17:11:33 | 显示全部楼层
这都是什么skill啊   下载来看看
发表于 2018-2-8 19:46:36 | 显示全部楼层
发表于 2018-2-9 08:47:47 | 显示全部楼层
发表于 2018-2-9 18:42:29 | 显示全部楼层
您需要登录后才可以回帖 登录 | 立即注册


Archiver|手机版|网站地图|Cadence Skill 论坛 ( 蜀ICP备13024417号|网站地图

GMT+8, 2018-3-17 14:09 , Processed in 0.362882 second(s), 38 queries , Gzip On.

Powered by Discuz! X3.2

© 2001-2013 Comsenz Inc.

快速回复 返回顶部 返回列表