Filename | Description |
assembly.il | Add assembly reference designators |
ruler.il | Add assembly rulers |
Auto_Balancing.il | Add filled rectangles on etch layer to provide balance during plating process |
addpinuse.il | Add pinuse codes from schematic as Allegro properties |
via_prop.il | Add a property to all vias on a net at once. |
fcircle.il | Add a filled circle to the active layer. |
text_add.il | Add text variables to the brd drawing automatically |
align_sym.il | Align symbols |
add_symbol.il | Allows user to add a symbol to the design (For Allegro 14.0) |
pickdata.il | Allegro to Capture backannotation of pick and place data |
cds2f.il | Allegro to Fabmaster extraction utility |
zrconnections.il | APD - Graphical interface to create the IO connections file used by ZRouter |
add_device_label.il | Assign DEVICE_LABEL property to components |
Associate_Components.il | Associate ICs and I/Os with bypass capacitors |
jbhEditBoard.il | Build a list of board files |
qfp_pitch.il | Calculate QFP pitch |
cwidth.il | Change Cline Widths /Layer/Width |
component_changes.il | Check component changes between boards |
via_pcs_check.il | Check vias on net against the vias listed in the constraint set |
dangling_lines.il | Check the status of the dangling line report |
Symbol_Check.il | Check if symbols exist |
conv.il | Convert between mils and mm |
cnv_height.il | Convert text height in mils to match the database units |
show_height.il | Copies the 14.x PACKAGE_HEIGHT_MIN/MAX properties to visible text for display and printing |
shape_push.il | Copy Shape to New Class or Subclass |
smd_pad_count.il | Count SMD pads in a design |
bbv_xsection.il | Create a graphical image of the board cross section showing via structures |
rep_bom_ignore.il | Create a report and add it to your report lists |
utl_sclass.il | Create a list of subclasses for given class |
runalgrplt.il | Create an Allegro plot |
mkdev.il | Create device files for use with third party netlist implementations |
Create_Thermal_Flash.il | Create Thermal Flash |
clinecut.il | Cut Clines By a Graphical Window Selection |
scalpel.il | Cut a channel through clines by drawing a path through them. |
cutshape.il | Cut/Split power rings in APD Package Designs |
prtobj.il | Debugging aid which recursively dumps dbid info to a file in hierarchical format |
dh_dummy_net.il | Dehighlight all Dummy nets in a design |
del_unconn.il | Delete unconnected shapes in 8.1 - Source code |
rm_nc_via.il | Delete all vias not on a net |
del_fp_prop.il | Delete Signal Integrity FP_* properties from Allegro symbols |
Find_DRC.il | Display all DRC markers for a layer |
drc_walk.il | Displays list of DRCs in a design and lets you "walk through" the list |
datasheet.il | Display utility for Datasheets using a URL |
pdi_vis.il | Display visibility control |
utl_distance.il | Distance between 2 pts or from 0,0 |
draw_targets.il | Draw targets to line up paper/film plots |
etch_visibility.il | Etch visibility |
comp_hght_rep.il | Extract component height to a file |
ipc_356.il | Extract a netlist in IPC-D-356 format |
solder_paste.il | Extract solder paste information |
bdct.zip | Fills class PACKAGE GEOMETRY/BODY_CENTER and draws circle with two diagonals in center of symbol |
find_dlines.il | Find all dangling clines and dangling lines |
mot_find_stubs.il | Find and identify stubs |
Find_Component.il | Find components from list |
height_check.il | Find components over, under or equal to a user specified height value |
show_library.il | Find library path of each Allegro symbol and create a report |
ood_shapes.il | Find out of date dynamic shapes in 15.0 and later |
flare_conn.il | Flare connects into vias and pins |
cdwIsPointInsideCircle.il | Function to determine whether a target point is within a circle |
replay.il | GUI to display scripts and replay them with a mouse click |
hl_npe.il | Highlight Missing Pin Escapes Skill 8.1 |
hl_ntp.il | Highlight Nets and Pins without Test Probes |
highlight_connected.il | Highlight only connected elements in a design |
highlight_padstack.il | Highlight padstacks from a list of component pin/via padstacks, and a list of drill sizes |
defineclass.zip | Initialize PADPATH variable for the manufacturing class you select |
net_editor.il | Interactive Net List Editor |
vcListBuilder.il | List building utility |
listratt.il | List all rat T points in a design |
thermal.il | Make a list of all the thermal flashes used in a padstack library |
slots.il | Make a list of all slots used in a padstack library |
padinshape.zip | Merge Cshapes with pads |
Mirror_Text.il | Mirror text |
nclegend_list.il | NCLEGEND List all NCLEGEND- subclasses in a design. |
NCP_drc.il | Place DRC markers on Device Pins that are missing a netname |
place_list.il | Place by List |
place_symbols.il | Place symbols and reference designators |
utl_ptaccur.il | Print number or point in design db accuracy |
myredraw.zip | Redraws one or more objects in a different class with the same coordinates; transforms clines into shapes |
killallxdrc.il | Remove all externally generated DRCs from the design |
strip_bad_fillet_props.il | Remove fillet properties on clines that are not actually fillets |
Rename_Ref_Des.il | Rename reference designators |
film_reorder.il | Reorder artwork films in the artwork control form |
replace_via.il | Replace Via padstack by window |
upd_fe_height.il | Replace PACKAGE_HEIGHT_MAX with value of HEIGHT property from ConceptHDL |
3d_length.il | Report 2d bonding wire to 3d length |
dp_rep.il | Report diff pair nets in a design. |
list1esc_length.il | Report first escape from pin, for Fully Buffered DIMM Design rule |
check_short_segs.il | Report short cline segments that are contained within the pad. |
build_ver.il | Report the product and version information of the currently running tool |
no_drc.il | Report and highlight pins with the NO_DRC property |
lfsViewReports.il | Report and Log File Viewer |
single_pin_net_check.il | Report and highlight single pin nets. |
autosize.il | Resize the drawing extents to match database objects |
dfa_assembly.il | Run DFA clearance checks referenced to the assembly subclass |
set_refdes.il | Save refdes locations from one file and read into another |
vc_SetOrigin.il | Set the design origin using mouse selection |
component_height.il | Show component heights |
autosilkUtils.il | Silkscreen violation checking utility |
tekTechFileXML.il | Techfile - Module to parse and import an XML Techfile |
rep_ucshape.il | Unconnected shape report |
mirrorvia.il | Utility to unmirror vias in a design. |
save_shape_drc.il | View DRC locations during shape cleanup after autovoid |
cdw_axlLineXLine.il | Workaround for the SKILL axlLineXLine() function which fails for vertical and horizontal segments |